Applied Materials Breakthrough in Chip Wiring Enables Logic Scaling to 3nm and Beyond
- Integrating seven process technologies in one system under vacuum cuts interconnect resistance in half
- New materials engineering approaches increase chip performance and reduce power consumption
- Latest system exemplifies Applied’s strategy to be the PPACt enablement company™ for customers
While size reduction benefits transistor performance, the opposite is true in the interconnect wiring: smaller wires have greater electrical resistance which reduces performance and increases power consumption. Without a materials engineering breakthrough, interconnect via resistance would increase by a factor of 10 from the 7nm node to the 3nm node, negating the benefits of transistor scaling.
“A smartphone chip has tens of billions of copper interconnects, and wiring already consumes a third of the chip’s power,” said
The Endura Copper Barrier Seed IMS system is now being used by leading foundry-logic customers worldwide. Additional information about the system and other innovations for logic scaling will be discussed at Applied’s 2021 Logic
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A photo accompanying this announcement is available at https://www.globenewswire.com/NewsRoom/AttachmentNg/5808956d-a82a-45d4-bb07-6e4804678159
Applied Materials' Endura® Copper Barrier Seed IMS™ System
Applied Materials’ new Endura® Copper Barrier Seed IMS™ combines seven different process technologies in one system under high vacuum to improve chip performance and power consumption. An animation of the process sequence can be viewed here: https://bit.ly/3g8HMe1.
Source: Applied Materials, Inc.